Thin film transistor device and method of manufacturing the same

ABSTRACT

A semiconductor film into which p-type impurities have been introduced is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry etching, the edge portion of the semiconductor film protrudes from the resist film. Next, the p-type impurities are introduced into the edge portion of the semiconductor film using the resist film as a mask. The volume density of the p-type impurities in a channel edge portion of the semiconductor film is two to five times the volume density of the p-type impurities in a channel center section. Subsequently, the resist film is removed to form a gate insulating film and a gate electrode.

CROSS-REFERENCE TO RELATED APLICATIONS

[0001] This application is based upon and claims priority of JapanesePatent Application No. 2002-053881, filed on Feb. 28, 2002, the contentsbeing incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a thin film transistor device inwhich thin film transistors using film of amorphous silicon, polysiliconor other semiconductor for an active layer are integrated and a methodof manufacturing the device.

[0004] 2. Description of the Prior Art

[0005] In recent years, a display for personal computers and atelevision, which use a liquid crystal display panel, have beengenerally used. The liquid crystal display panel is also used for adisplay of cell phones, PDAs (Personal Digital Assistant), and the like.Further, development of an organic EL display panel, which can save morepower than the liquid crystal display panel, is in progress as well inrecent years, and the organic EL display panel has already beencommercialized in some products.

[0006] In the liquid crystal display panel and the organic EL displaypanel, a large numbers of picture elements (sub pixels) are generallyarrayed in a matrix state, and each picture element is provided with athin film transistor (hereinafter, also referred to as TFT) as aswitching element. A display panel having such a structure is referredto as an active matrix display panel.

[0007] A general TFT is provided with a semiconductor film formed on aninsulated substrate, a gate insulating film formed on the semiconductorfilm, and a gate electrode formed on the gate insulating film. However,positions of the gate electrode and the semiconductor film are oppositein the case of an inversely staggered TFT.

[0008] When an amorphous silicon film is used as the semiconductor film,it is necessary that an IC (Integrated Circuit) for panel driving beconnected outside the display panel and the IC for panel driving drivethe display panel because carrier mobility of amorphous silicon issmall. On the other hand, when a polysilicon film is used as thesemiconductor film, a drive circuit constituted by TFTs can beintegrally formed on the display panel because carrier mobility of thepolysilicon film is large. This reduces the number of parts and thenumber of manufacturing processes of an apparatus using the displaypanel, and a product cost can be reduced.

[0009]FIGS. 1A to 1C are views showing the structure of a conventionalTFT, where FIG. 1A, 1B and 1C are a plan view of the TFT, a sectionalview at I-I line in FIG. 1A, and a sectional view at II-II line in FIG.1A, respectively.

[0010] A silicon oxide film as an underlying insulating film 11 isformed on a glass substrate (insulated substrate) 10. The polysiliconfilm as a semiconductor film 12 is formed on a TFT formation region ofthe underlying insulating film 11.

[0011] The silicon oxide film as a gate insulating film 13 is formed onthe underlying insulating film 11 and the semiconductor film 12, and agate electrode 14 made of metal is formed on the gate insulating film13. The gate electrode 14 is formed so as to cross above thesemiconductor film 12.

[0012] A pair of highly concentrated impurity regions (source/drainregions) 12 a, 12 b, which have been formed by implanting p-type orn-type impurities using the gate electrode 14 as a mask, are providedfor the semiconductor film 12.

[0013] Incidentally, in the case of the TFT, where the semiconductorfilm 12 is made up of polysilicon and the gate insulating film 13 ismade up of silicon oxide as shown in this example, it is known that athreshold voltage is negative (a few −V) if dopant (impurities) is notadded at all to a channel region of the semiconductor film 12.

[0014] Since CMOS (Complimentary Metal Oxide Semiconductor) where thep-type TFT and the n-type TFT are arranged in a pair is used in thedrive circuit of the display panel, a leakage current occurs to increasepower consumption unless the threshold value voltage is adjusted suchthat both of the p-type TFT and the n-type TFT are turned off when agate voltage is 0V. For this reason, the p-type impurities such as boron(B) is introduced into the entire semiconductor film 12 before formingthe gate electrode 14 to control the threshold voltage such that boththe p-type TFT and the n-type TFT are turned off when the gate voltageis 0V.

[0015] There exist an ion implantation method, an ion doping method, anda vapor-phase doping method, for example, as a method to introduce thep-type impurities into the semiconductor film 12. Note that, in thepresent invention, a method in which mass separation is performed andonly a target ion is implanted into the semiconductor film is referredto as the ion implantation method, and a method in which the impuritiesare accelerated without performing mass separation and implanted intothe semiconductor film is referred to as the ion doping method. As theion doping method, there exists a method in which material gas such asdiborane (B₂H₆), for example, is excited by RF (Radio Frequency) powerto generate boron ion and the boron ion is accelerated into energyhaving a few keV to 100 keV to be implanted into the semiconductor film.Further, as the ion doping method, there exists a method in which ion isgenerated by ark discharge using filament instead of the above-describedRF electric power and the ion is accelerated to be implanted into thesemiconductor film, or a method in which ion beam generated by the arkdischarge is implanted into the semiconductor film while scanning thebeam.

[0016] The following method is used in the case of forming thepolysilicon film containing boron (B) as the p-type impurities by thevapor-phase doping method.

[0017] First, after having formed the underlying insulating film 11 onthe substrate 10, the amorphous silicon film is formed on the underlyinginsulating film 11 by a plasma CVD (Chemical Vapor Deposition) method.At this point, diborane (B₂H₆) gas is mixed into silane (SiH₄) gas,which is a material, to form the amorphous silicon film containing boron(B).

[0018] Subsequently, laser is irradiated onto the amorphous silicon filmto transform the silicon into polycrystalline. Thus, the polysiliconfilm containing boron is obtained. Then, patterning is performed to thepolysilicon film into a predetermined shape.

[0019] In the vapor-phase doping method, boron quantity per unit volume(volume density) in a film thickness direction of the semiconductor filmbecomes uniform.

[0020] The following method is used in the case of forming thepolysilicon film into which the p-type impurities have been introducedby the ion implantation method or the ion doping method.

[0021] First, after having formed the underlying insulating film 11 onthe substrate 10, the amorphous silicon film is formed on the underlyinginsulating film 11 by the plasma CVD method. Subsequently, laser isirradiated onto the amorphous silicon film to transform the silicon intopolycrystalline, and the polysilicon film is obtained.

[0022] Next, patterning is performed to the polysilicon film into apredetermined shape by the photolithography method. Then, ionimplantation or ion doping of boron (B) as the p-type impurities, forexample, are performed to the polysilicon film.

[0023] However, the inventors think that the above-describedconventional manufacturing method of TFT has the following problems.

[0024] Generally, in the TFT used in the liquid crystal display panel orthe like, the edge portion of the semiconductor film is processed so asto have gradient as shown in FIG. 1C for the purpose of securingwithstand voltage for the gate insulating film 13 (refer to PatentApplication Publication (KOKAI) 2000-31493, for example). Hereinafter,the gradient portion of the silicon film is referred to as a gradientsection.

[0025] As described above, since the boron quantity per unit volume(volume density) in the film thickness direction of the semiconductorfilm is uniform in the vapor-phase doping method, the boron quantity(surface density) per unit area of the gradient section in the channelregion is smaller than that of a central section (hereinafter, alsoreferred to as a flat section) of the channel region when the TFT isviewed from above. Accordingly, the threshold voltage at the gradientsection becomes lower than the threshold value voltage at the flatsection by approximately −1V to −2V.

[0026]FIG. 2 is the view schematically showing the current-voltagecharacteristic (I-V characteristic) of the conventional TFT (n-type TFTand p-type TFT). As shown in FIG. 2, the gradient section of the n-typeTFT has a small channel width and becomes a parasitic transistor with alow threshold value voltage, and the current actually flowing in the TFTis one where the characteristic of the gradient section is added to thecharacteristic of the flat section, which is the characteristic having aso-called hump. Note that, in the p-type TFT, the characteristic of thegradient section is masked by the characteristic of the flat section,and a change of the threshold voltage due to the influence of thegradient section does not occur.

[0027] In the case where the n-type TFT and the p-type TFT having suchcharacteristics constitute the CMOS, it is difficult to control a dopingquantity of the p-type impurities into the semiconductor film such thatboth TFTs are turned off when the gate voltage is 0V because thethreshold of the n-type TFT and the threshold of the p-type TFT areclose.

[0028] Although distribution of the p-type impurities are not uniform inthe thickness direction of the semiconductor film when the polysiliconfilm, into which the p-type impurities was introduced by the ionimplantation method or the ion doping method, has been formed, thesurface density of the p-type impurities of the gradient section becomessmaller than that of the flat section, which is the same as the case ofthe vapor-phase doping method. Furthermore, a problem similar to the onedescribed above occurs in the inverted staggered TFT as well when theedge portion of the semiconductor film is gradient.

[0029] Note that Patent Application Publication (KOKAI) 2000-77665proposes that ion implantation of Ar be performed to the edge portion ofthe polysilicon film to give damage thereto into an amorphous state, anda drive capability of the parasitic transistor be reduced. However, itis considered that annealing in a post-process causes recrystallizationdepending on the concentration of Ar and the influence of the edgeportion may appear.

SUMMARY OF THE INVENTION

[0030] The object of the present invention is to provide a thin filmtransistor device in which both the n-type TFT and the p-type TFT areturned off at a predetermined gate voltage (0V for example) and thepower consumption can be reduced comparing to the conventional device,and a method of manufacturing the device.

[0031] The thin film transistor device according to the first aspect ofthe present invention comprises: a substrate; and a thin film transistorformed above the substrate and has a semiconductor film, where thep-type impurities have been introduced in the channel region, as theoperation layer, in which the gradient is provided for the edge portionof the semiconductor film and the volume density of the p-typeimpurities in the edge portion of the channel region is twice to fivetimes the volume density of the p-type impurities in the central sectionof the channel region.

[0032] In the present invention, the volume density of the p-typeimpurities in the edge portion of the channel region is as high as twiceto five times the volume density of the p-type impurities in the centralsection of the channel region. This makes the surface density of thep-type impurities in the edge portion of the channel region becomesubstantially equal to the surface density of the p-type impurities inthe central section of the channel region, and the threshold voltage ofthe parasitic transistor formed at the gradient section increases. As aresult, the hump in the I-V characteristic of the n-type thin filmtransistor disappears, and both the n-type thin film transistor and thep-type thin film transistor can be turned off at the predetermined gatevoltage.

[0033] The method of manufacturing the thin film transistor according tothe second aspect of the present invention comprises the steps of:forming the semiconductor film, into which the p-type impurities havebeen introduced, above the substrate; forming a resist film on a thinfilm transistor formation region of the semiconductor film; etching inwhich the semiconductor film is etched using the resist film as a mask;introducing the p-type impurities into a portion of the semiconductorfilm, which protrudes from the resist film, using the resist film as amask; removing the resist film; forming the gate insulating film; andforming the gate electrode.

[0034] In the present invention, after having formed the semiconductorfilm above the substrate and having formed the resist film on thesemiconductor film, dry etching using gas containing SF₆ and oxygen, forexample, is performed to the semiconductor film using the resist film asa mask. At this point, when a positive type resist is used, for example,the edge portion of the resist film generally has gradient such that thewidth becomes smaller from the bottom portion to the upper portion.Then, the edge portion of the resist film withdraws with the progress ofetching to the semiconductor film, and the edge portion of thesemiconductor film protrudes from the resist film. Further, the portionof the semiconductor film, which has protruded from the resist filmbecomes gradient.

[0035] Subsequently, the p-type impurities are introduced into the edgeportion (gradient section) of the semiconductor film using the resistfilm as a mask. Thus, the semiconductor film having higher volumedensity of the p-type impurities in the edge portion than the volumedensity of the p-type impurities in the central section is obtained. Inthe case of a coplanar TFT, after having removed the resist filmsubsequently, the gate insulating film and the gate electrode are formedon the semiconductor film. The thin film transistor without a hump inthe I-V characteristic can be formed in this manner. Note that thesemiconductor film is formed after having formed the gate electrode andthe gate insulating film in the case of the inversely staggered TFT.

[0036] The method of manufacturing the thin film transistor according tothe third aspect of the present invention comprises the steps of:forming the semiconductor film, into which the p-type impurities havebeen introduced, above the substrate; forming a mask film on thesemiconductor film; forming the resist film on the thin film transistorformation region of the mask film; etching the mask film and thesemiconductor film using the resist film as a mask; removing the resistfilm; introducing the p-type impurities into a portion of thesemiconductor film, which has protruded from the mask film, using themask film as a mask; forming the gate insulating film; and forming thegate electrode.

[0037] In the present invention, the mask film is formed on thesemiconductor film, and the resist film is further formed thereon. Then,dry etching, for example, is performed to the semiconductor film and themask film using the resist film as a mask. In this step, the edgeportion of the resist film has gradient and the edge portion of theresist film withdraws with progress of etching. Then, the edge portionof the semiconductor film protrudes from the resist film and the maskfilm.

[0038] Subsequently, the resist film is removed, and the p-typeimpurities are introduced into the edge portion of the semiconductorfilm using the mask film as a mask. Thus, the semiconductor film havinghigher volume density of the p-type impurities in the edge portion thanthe volume density of the p-type impurities in the central section isobtained.

[0039] In the present invention, the resist film can be removed byremover because the impurities are not implanted into the resist film.Accordingly, operation is easier comparing with the case where theresist film is removed by ashing.

[0040] The method of manufacturing the thin film transistor according tothe fourth aspect of the present invention comprises the steps of:forming the semiconductor film above the substrate; forming the maskfilm on the semiconductor film; forming the resist film on the thin filmtransistor formation region of the mask film; etching the mask film andthe semiconductor film using the resist film as a mask; removing theresist film; introducing the p-type impurities into the entiresemiconductor film on condition that the impurities transmit through themask film; introducing the p-type impurities into only a part of thesemiconductor film, which has protruded from the mask film, on conditionthat the impurities are blocked by the mask film; forming the gateinsulating film; and forming the gate electrode. Note that the order ofthe step of introducing the p-type impurities into the entiresemiconductor film on condition that the impurities transmit through themask film and the step of introducing the p-type impurities into only apart of the semiconductor film, which has protruded from the mask film,on condition that the impurities are blocked by the mask film may beopposite.

[0041] In the present invention, the mask film is formed on thesemiconductor film, and the resist film is formed on the mask film.Then, etching is performed to the semiconductor film and the mask filmusing the resist film as a mask. Thus, the semiconductor film protrudesfrom the resist film. Subsequently, after having removed the resistfilm, the p-type impurities are introduced into the entire semiconductorfilm on condition that the impurities transmit through the mask film,and furthermore, the p-type impurities are introduced into only a partof the semiconductor film, which has protruded from the mask film, oncondition that the impurities are blocked by the mask film. With thisprocedure, the semiconductor film having higher volume density of thep-type impurities in the edge portion than the volume density of thep-type impurities in the central section.

[0042] The thin film transistor device according to the fifth aspect ofthe present invention comprises: the substrate; and a thin filmtransistor that is formed above the substrate and has a semiconductorfilm, where the p-type impurities have been introduced at least into thechannel region, as the operation layer, in which the gradient isprovided for the edge portion of the semiconductor film and the p-typeimpurities have been introduced into the channel region of thesemiconductor film such that a peak of distribution appears in thevicinity of the surface.

[0043] In the present invention, since the p-type impurities have beenintroduced into the channel region of the semiconductor film such thatthe peak of distribution appears in the vicinity of the surface, thesurface density of the p-type impurities when the thin film transistoris viewed from above becomes substantially the same in the edge portionand the central section of the channel region. Although the surfacedensity is low at a gradient tip portion of a channel edge portionbecause a film thickness becomes thin, electric current that flows inthis portion is small as well and formation of the hump in the I-Vcharacteristic is avoided.

[0044] Accordingly, both the n-type thin film transistor and the p-typethin film transistor can be turned off at the predetermined gatevoltage.

[0045] The method of manufacturing the thin film transistor according tothe sixth aspect of the present invention comprises the steps of:forming the semiconductor film above the substrate; forming the resistfilm on the thin film transistor formation region of the semiconductorfilm; etching the semiconductor film using the resist film as a mask;removing the resist film; introducing the p-type impurities into thesemiconductor film on condition that the peak of distribution appears inthe vicinity of the surface of the semiconductor film; forming the gateinsulating film; and forming the gate electrode.

[0046] In the present invention, since the p-type impurities areintroduced into the semiconductor film on condition that the peak ofdistribution appears in the vicinity of the surface of the semiconductorfilm, the surface density of the p-type impurities becomes substantiallythe same in the edge portion and the central section of the channelregion. Accordingly, both the n-type thin film transistor and the p-typethin film transistor can be turned off at the predetermined gatevoltage.

[0047] The thin film transistor device according to the seventh aspectof the present invention comprises: the substrate; and the p-type thinfilm transistor and the n-type thin film transistor, which are formedabove the substrate, in which both the p-type thin film transistor andthe n-type thin film transistor have the semiconductor film, which isprovided with the gradient at the edge portion, as the operation layer,the volume density of the p-type impurities contained in the channelregion of the semiconductor film of the n-type thin film transistor ishigher than the volume density of the p-type impurities in the channelregion of the semiconductor film of the p-type thin film transistor, andthe volume density of the p-type impurities in the gradient section ofthe channel region of the n-type thin film transistor is twice or morethe volume density of the p-type impurities in the central section ofthe channel region.

[0048] In the present invention, the impurities are introduced into thegradient section of the channel region of the n-type thin filmtransistor in the volume density of twice or more that of the centralsection of the channel region. Further, more quantity of the p-typeimpurities are introduced into the channel region of the n-type thinfilm transistor than the channel region of the p-type thin filmtransistor.

[0049] Thus, the threshold of the n-type thin film transistor increases,and the difference between the thresholds of the p-type thin filmtransistor and the n-type thin film transistor becomes larger. As aresult, implantation quantity of impurities for threshold control iseasily controlled, and both the n-type thin film transistor and thep-type thin film transistor can be turned off at the predetermined gatevoltage.

[0050] The method of manufacturing the thin film transistor according tothe eighth aspect of the present invention comprises the steps of:forming the semiconductor film, into which the p-type impurities havebeen introduced, above the substrate; forming the mask film on thesemiconductor film; forming a first resist film on a p-type thin filmtransistor formation region and an n-type thin film transistor formationregion of the mask film; etching the semiconductor film and the maskfilm using the first resist film as a mask; removing the first resistfilm; covering the p-type thin film transistor formation region abovethe substrate with a second resist film; introducing the p-typeimpurities into the entire semiconductor film of the n-type thin filmtransistor formation region on condition that the impurities transmitthrough the mask film, and introducing the p-type impurities into a partof the semiconductor film in the n-type thin film transistor formationregion, which has protruded from the mask film, on condition that theimpurities are blocked by the mask film; removing the second resistfilm; forming the gate insulating film; and forming the gate electrode.

[0051] In the present invention, after having formed the semiconductorfilm and the mask film above the substrate, etching is performed to thesemiconductor film and the mask film using the first resist film as amask. In this step, the edge portion of the semiconductor film becomesgradient and the gradient portion protrudes from the resist film and themask film. Subsequently, after having removed the first resist film, thesecond resist film that covers the p-type thin film transistor formationregion is formed. Then, the p-type impurities are introduced into theentire semiconductor film in the n-type thin film transistor formationregion on condition that the impurities transmit through the mask film.Moreover, the p-type impurities are introduced into a part of thesemiconductor film, which has protruded from the mask film, on conditionthat the impurities are blocked by the mask film. Accordingly, the humpin the I-V characteristic of the n-type thin film transistor disappears,and the difference between the threshold of the p-type thin filmtransistor and the threshold of the n-type thin film transistor becomeslarger. As a result, both the n-type thin film transistor and the p-typethin film transistor can be turned off at the predetermined gatevoltage.

[0052] Note that, in the present invention, the order of the step ofintroducing the p-type impurities into the entire semiconductor film andthe step of introducing the p-type impurities into a part of thesemiconductor film, which has protruded from the mask film, may beexecuted in an opposite order.

BRIEF DESCRIPTION OF THE DRAWINGS

[0053]FIGS. 1A, 1B, and 1C are a plan view of a TFT, a sectional view ofFIG. 1A at I-I line, and a sectional view of FIG. 1A at II-II line,respectively.

[0054]FIG. 2 is a view schematically showing the I-V characteristic of aconventional TFT (n-type TFT and p-type TFT).

[0055]FIG. 3 is a block diagram showing a constitution of the thin filmtransistor device (transmissive liquid crystal display panel) of thefirst embodiment of the present invention.

[0056]FIG. 4 is a sectional view of a display section of the liquidcrystal display panel of the first embodiment of the present invention.

[0057]FIG. 5 is a plan view of a TFT substrate on the display section.

[0058]FIG. 6 is a plan view of the TFT formation section.

[0059]FIG. 7 is a sectional view of FIG. 6 at III-III line.

[0060]FIGS. 8A to 8E are sectional views showing a manufacturing methodof the TFT substrate according to the first embodiment, and aresectional views of FIG. 6 at the position of III-III line.

[0061]FIGS. 9A to 9E are sectional views showing manufacturing method ofthe TFT substrate according to the first embodiment, and are sectionalviews of FIG. 6 at the position of IV-IV line.

[0062]FIGS. 10A to 10C are enlarged sectional views showing a method ofintroducing impurities into the gradient section of semiconductor film.

[0063]FIG. 11 is a view showing the I-V characteristic of the p-type TFTand the n-type TFT according to the first embodiment.

[0064]FIG. 12 is a view showing the I-V characteristic when impurityconcentration per unit volume at the gradient section of the channelregion has exceeded five times the impurity concentration at the flatsection.

[0065]FIGS. 13A to 13C are sectional views showing the manufacturingmethod of the thin film transistor device of the second embodiment ofthe present invention in the order of process.

[0066]FIG. 14 is a sectional view showing a variation example of thesecond embodiment.

[0067]FIGS. 15A to 15C are sectional views showing the manufacturingmethod of the TFT of the third embodiment according to the presentinvention in the order of process.

[0068]FIG. 16 is a view showing the I-V characteristic when the quantityof p-type impurities in the channel region of the n-type TFT is largerthan the quantity of p-type impurities in the channel region of thep-type TFT.

[0069]FIGS. 17A to 17D are sectional views showing the manufacturingmethod of the thin film transistor of the fourth embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0070] In the following, embodiments of the present invention will bedescribed with reference to the accompanying drawings.

[0071] (First Embodiment)

[0072]FIG. 3 is the block diagram showing a constitution of the thinfilm transistor device (a transmissive liquid crystal display panel) ofthe first embodiment of the present invention. Note that descriptionwill be made for the liquid crystal display panel having an XGA(1024×768 pixels) mode.

[0073] The liquid crystal display panel of this embodiment is providedwith a control circuit 101, a data driver 102, a gate driver 103, and adisplay section 104. An external device (not shown) such as a computersupplies signals such as display signal RGB (R: red signal, G: greensignal, B: blue signal), horizontal synchronizing signal (Hsync), andvertical synchronizing signal (Vsync), and a power source (not shown)supplies high voltage VH (18V, for example), low voltage VL (3.3V or 5V,for example), and ground potential Vgnd to the liquid crystal displaypanel.

[0074] Picture elements (sub pixels) of 3072 (1024×RGB) pieces in ahorizontal direction and 768 pieces in a vertical direction are arrayedon the display section 104. One picture element is provided with ann-type TFT 105, a display cell 106 connected to the source electrode ofthe n-type TFT 105, and a storage capacitor 107. The display cell 106 isprovided with a pair of electrodes, liquid crystal between theelectrodes, a polarizer and a color filter respectively arranged on andunder a pair of the electrode, and the like.

[0075] Further, 3072 data bus lines 108 extending in a verticaldirection and 768 gate bus lines 109 extending in a horizontal directionare provided for the display section 104. The gate electrode of each TFT105 of picture elements arrayed in a horizontal direction is connectedto the same gate bus line 109, and a drain electrode of each TFT 105arrayed in a vertical direction is connected to the same data bus line108.

[0076] The control circuit 101 receives the horizontal synchronizingsignal (Hsync) and the vertical synchronizing signal (Vsync), andoutputs data start signal DSI activated at a starting point of onehorizontal synchronizing period, data clock DCLK that divides onehorizontal synchronizing period into regular intervals, gate startsignal GSI activated at a starting point of one vertical synchronizingperiod, and gate clock GCLK that divides one vertical synchronizingperiod into regular intervals.

[0077] The data driver 102 is provided with a shift register 102 a, alevel shifter 102 b, and an analog switch 102 c.

[0078] The shift register 102 a has 3072 pieces of output terminals. Theshift register 102 a is initialized by the data start signal DSI, andsequentially outputs low-voltage active signal from each output terminalwith timing synchronous with the data clock DCLK.

[0079] The level shifter 102 b includes 3072 pieces of input terminalsand 3072 pieces of output terminals. The level shifter 102 b convertsthe low-voltage active signal output from the shift resister 102 a intohigh-voltage and outputs it.

[0080] The analog switch 102 c also includes 3072 pieces of inputterminals and 3072 pieces of output terminals. Each output terminal ofthe analog switch 102 c is severally connected to a corresponding databus line 108. When the analog switch 102 c has received the activesignal from the level shifter 102 b, it outputs the display signal RGB(any one of R signal, G signal, and B signal) to an output terminalcorresponding to the input terminal that has received the active signal.

[0081] Specifically, the data driver 102 outputs the R signal, the Gsignal, and the B signal sequentially to the 3072 data bus lines 108 ofthe display section 104 in timing synchronous with the data clock DCLKin one horizontal synchronizing period.

[0082] The gate driver 103 is provided with a shift register 103 a, alevel shifter 103 b, and an output buffer 103 c.

[0083] The shift register 103 a has 768 pieces of output terminals. Theshift register 103 a is initialized by the gate start signal GSI, andsequentially outputs low-voltage scanning signal from each outputterminal with timing synchronous with the gate clock GCLK.

[0084] The level shifter 103 b includes 768 pieces of input terminalsand 768 pieces of output terminals. Then, the level shifter 103 bconverts the low-voltage scanning signal received from the shiftresister 103 a into high-voltage and outputs it.

[0085] The output buffer 103 c also includes 768 pieces of inputterminals and 768 pieces of output terminals. Each output terminal ofthe output buffer 103 c is severally connected to a corresponding gatebus line 109. The output buffer 103 c supplies the scanning signalreceived from the level shifter 103 b to the gate bus line 109 via anoutput terminal corresponding to the input terminal.

[0086] Specifically, the gate driver 103 supplies the scanning signalsequentially to the 768 gate bus lines 109 of the display section 104 intiming synchronous with the gate clock GCLK in one verticalsynchronizing period.

[0087] The TFTs 105 of the display section 104 turn on when the scanningsignal is supplied to the gate bus lines 109. At this point, when thedisplay signal RGB (any one of R signal, G signal, and B signal) issupplied to the data bus lines 108, the display signal RGB is written tothe display cells 106 and the storage capacitors 107. In the displaycells 106, orientation of liquid molecules change due to the displaysignal RGB that has been written, and light transmittance of the displaycells 106 changes as a result. By controlling the light transmittance ofthe display cells 106 for each picture element, a desired image isdisplayed.

[0088] In this embodiment, the TFTs 105 in the picture elements are then-type as described above. Further, the control circuit 101, the datadriver 102, and the gate driver 103 are provided with the p-type TFTsand the n-type TFTs.

[0089]FIG. 4 is the sectional view of the display section of the liquidcrystal display panel of the first embodiment of the present invention,and FIG. 5 is the plan view of the TFT substrate on the display section.Although the storage capacitor 107 shown in FIG. 3 is actually formed ineach picture element, illustration and description thereof are omittedhere.

[0090] The liquid crystal display panel of this embodiment is providedwith a TFT substrate 120 and a CF substrate 150 arranged opposing toeach other, and liquid crystal 180 filled between the TFT substrate 120and the CF substrate 150 as shown the sectional view of Fig.4.

[0091] The TFT substrate 120 is provided with a glass substrate (atransparent insulated substrate) 121, and the data bus lines 108, thegate bus lines 109, the TFTs 105, picture element electrodes 129 and thelike, which have been formed on the glass substrate 121. In thisembodiment, a part of the gate bus line 109 is a gate electrode of theTFT 105 as shown in FIG. 5, and a source electrode 127 a for the TFT 105is connected to the picture element electrode 129, and a drain electrode127 b is connected to the data bus line 108. Further, an alignment film131 is formed on the picture element electrodes 129.

[0092] Moreover, the n-type TFTs, the p-type TFTs, wirings, and the likeare formed outside the display section of the TFT substrate 120, whichconstitute the control circuit 101, the data driver 102, and the gatedriver 103 (drive circuit).

[0093] On the other hand, the CF substrate 150 is provided with a glasssubstrate (transparent insulated substrate) 151, a black matrix 152formed on the glass substrate 151, a color filter 153, and a commonelectrode 154. The black matrix 152 is formed so as to cover the regionamong the picture elements and the TFT formation region. Further, thecolor filter 153 having any one of red, green and blue is formed on eachpicture element. In this embodiment, the common electrode 154 is formedon the color filter 153, and the surface of the common electrode 154 iscovered with an orientation film 155.

[0094] The TFT substrate 120 and the CF substrate 150 are arranged bymaking the surfaces, on which the alignment films (131, 155) have beenformed, oppose to each other.

[0095]FIG. 6 is the plan view of the TFT formation section, and FIG. 7is the sectional view of FIG. 6 at the position of III-III line.Description will be further made for the constitution of the TFTsubstrate 120 referring to FIG. 6 and FIG. 7. Note that illustration ofthe alignment film 131 is omitted in FIGS. 6 and 7.

[0096] An underlying insulating film 122 is formed on the glasssubstrate 121. A polysilicon film 123, which is the operation layer forthe TFTs 105, is formed on a predetermined region of the underlyinginsulating film 122.

[0097] A pair of high-concentration impurity regions (123 a, 123 b),which are source/drain for TFTs 105, are formed in the polysilicon film123 sandwiching the channel region. In this embodiment, the gradient isprovided for the edge portion of the polysilicon film 123, as shown inFIG. 7. Then, the p-type impurities are introduced into the channelregion of the polysilicon film 123 for controlling the threshold value,and the p-type impurities are introduced into the edge portion (gradientsection) of the polysilicon film 123 in the volume density twice to fivetimes that of the central section (flat section) of the channel region.

[0098] A gate insulating film 124 is formed on the channel region of thepolysilicon film 123, and a gate electrode 125 (gate bus line 109) isformed on the gate insulating film 124.

[0099] A first interlayer insulating film 126 is formed on theunderlying insulating film 122 and the gate electrode 125 (gate bus line109). A source electrode 127 a, a drain electrode 127 b, and the databus line 108 are formed on the fist interlayer insulating film 126. Thesource electrode 127 a is electrically connected to thehigh-concentration impurity region 123 a via a contact hole 126 aprovided for the first interlayer insulating film 126, and the drainelectrode 127 b is electrically connected to the high-concentrationimpurity region 123 b via a contact hole 126 b provided for the firstinterlayer insulating film 126.

[0100] A second interlayer insulating film 128 is formed on the firstinterlayer insulating film 126, the data bus line 108, the sourceelectrode 127 a, and the drain electrode 127 b, and the picture elementelectrode 129 made up of transparent conductor such as ITO (Indium-TinOxide) is formed on the second interlayer insulating film 128. Thepicture element electrode 129 is electrically connected to the sourceelectrode 127 a via a contact hole 128 a provided for the secondinterlayer insulating film 128.

[0101]FIGS. 8A to 8E and FIGS. 9A to 9E are the sectional views showingthe manufacturing method of the TFT substrate having the above-describedstructure in the order of process. Note that FIGS. 8A to 8E show thesectional views of FIG. 6 at the position of III-III line, and FIGS. 9Ato 9E show the sectional views of FIG. 6 at the position of IV-IV line.

[0102] First, as shown in FIG. 8A and 9A, the glass substrate 121 as theinsulated substrate is prepared, an underlying insulating film 122 madeup of silicon oxide film (SiO₂), for example, is formed on the glasssubstrate 121 in the thickness of approximately 100 nm. Subsequently, anamorphous silicon film 123 a containing boron (B), which is the p-typeimpurities, is formed on the underlying insulating film 122 in thethickness of approximately 40 nm by the vapor-phase doping method usinga CVD system. The volume density of boron in the amorphous silicon film123 a is set to 4×10¹⁷ cm⁻³, for example.

[0103] Next, as shown in FIG. 8B and FIG. 9B, excimer laser isirradiated over the entire upper surface of the glass substrate 121 tocrystallize the surface, and the amorphous silicon film 123 a is changedto the polysilicon film 123. Then, a resist film R1 is formed on apredetermined region (TFT formation region) of the polysilicon film 123using the positive type photoresist.

[0104] Next, the glass substrate 121 is placed in a dry etching system(not shown). Then, SF₆ and oxygen gas, for example, are introduced inthe etching system to perform dry etching to the polysilicon film 123using the resist film R1 as a mask. At this point, as shown in FIG. 10A,gradient whose width becomes smaller generally from the bottom portionto the upper portion is created at the edge portion of the resist filmR1, and the gradient surface gradually withdraws as it is etched inplasma containing oxygen, as shown in Fig. 10B. With this withdrawal,gradient is created at the edge portion of the polysilicon film 123 aswell as shown in FIG. 8C and FIG. 9C. The polysilicon film 123 havingthe gradient at the edge portion is formed in this manner.

[0105] Next, boron is implanted into the polysilicon film 123 using anion doping system on condition that acceleration voltage is 5 kV, dosageis 2×10¹² cm⁻². Accordingly, boron is not introduced into a part of thepolysilicon film 123, which is masked by the resist film R1, boron isselectively introduced only into the edge portion (gradient section) ofthe polysilicon film 123 as shown in FIG. 10C. The volume density ofboron in the gradient section of the polysilicon film 123 isapproximately 1×10¹⁸ cm⁻³ together with the one created in the previousvapor-phase doping. This density is equivalent to approximately 2.5times the volume density of boron in the channel flat section.

[0106] Incidentally, when the edge portion of the polysilicon film 123is not sufficiently exposed from the resist film R1 after dry etching,the resist film R1 is entirely etched in oxygen plasma, for example, tomake the edge portion of the resist film R1 withdraw, and thepolysilicon film 123 may be sufficiently exposed.

[0107] After boron has been introduced only into the gradient section ofthe polysilicon film 123 in this manner, resist film R1 is removed byplasma ashing or the like.

[0108] Next, an SiO₂ film that is the gate insulating film 124 is formedin the thickness of approximately 100 nm on the polysilicon film 123.Subsequently, an aluminum film is formed on the SiO₂ film by asputtering method, for example, in the thickness of approximately 400nm. Then, patterning is performed to the aluminum film and the SiO₂ filmby the photolithography method to form the gate electrode 125 (gate busline 109) and the gate insulating film 124.

[0109] Note that predetermined wirings (first layer wirings) are formedsimultaneously with forming the gate electrode 125 in a dive circuitformation region outside the display section.

[0110] Next, ion implantation of phosphorous (P) as the n-typeimpurities is performed into the polysilicon film 123 using the gateelectrode 125 as a mask to form a pair of the high-concentrationimpurity regions (123 a, 123 b) that become source/drain. At this point,a so-called LDD (Lightly Doped Drain) region having low impurityconcentration may be formed between the high-concentration impurityregions (123 a, 123 b) and the channel region.

[0111] After having formed the n-type TFT in this manner, the resistfilm where only the p-type TFT formation region is exposed is formed onthe glass substrate 121. Then, ion implantation of boron, for example,as the p-type impurities is performed into the polysilicon film 123 inthe p-type TFT formation region in the concentration twice or more thatof phosphorous (P) previously implanted, and thus the p-type TFT isformed. According to this method, the n-type TFT and the p-type TFT canbe formed with a relatively small number of processing.

[0112] Alternatively, ion implantation of the p-type impurities ispreviously performed to the polysilicon film 123 in the n-type TFTformation region and the p-type TFT formation region. And then, thep-type TFT formation region is covered with the resist film, the n-typeimpurities are implanted into the n-type TFT formation region in theconcentration twice or more that of the p-type impurities, and then-type TFT thus may be formed.

[0113] Next, thermal treatment is performed at 300° C. to 600° C. toactivate the impurities implanted into the polysilicon film 123. Theimpurities may be activated by processing such as laser irradiation orlamp anneal instead of regular thermal treatment.

[0114] Next, as shown in FIG. 8E and FIG. 9E, a silicon nitride film(SiN) having the thickness of 400 nm as the first interlayer insulatingfilm 126 is formed over the entire upper surface of the substrate 121,and the contact holes (126 a, 126 b) reaching the high-concentrationimpurity regions (123 a, 123 b) from the surface of the first interlayerinsulating film 126 are formed.

[0115] Next, Ti (30 nm), Al (300 nm), and Mo (50 nm) are formed in thisorder to form a metal layer of a three-layer structure. Then, patterningis performed to the metal film to form the data bus line 108, the sourceelectrode 127 a, and the drain electrode 127 b.

[0116] At this point, predetermined wirings (second layer wirings) areformed simultaneously in the drive circuit formation region outside thedisplay section.

[0117] Next, as shown in FIG. 7, the silicon nitride film or the siliconoxide film is formed as the second interlayer insulating film 128 overthe entire upper surface of the substrate 121 in the thickness of 200 nmto 300 nm, and the contact hole 128 a is formed at a predeterminedposition of the second interlayer insulating film 128. Note that organicresin may be used as material of the second interlayer insulating film128, and two or more kinds of film out of the silicon nitride film, thesilicon oxide film, and organic resin film may be laminated to form thesecond interlayer insulating film 128.

[0118] Subsequently, the ITO film is formed over the entire uppersurface of the substrate 121, and patterning is performed to the ITOfilm to form the picture element electrode 129. The picture elementelectrode 129 is electrically connected to the source electrode 127 avia the contact hole 128 a.

[0119] The TFT substrate manufactured in this manner and the CFsubstrate, on which the color filter, the common electrode, and the likehave been formed, are arranged opposing to each other, liquid crystal isfilled between the both substrates, and thus completing the liquidcrystal display panel.

[0120]FIG. 11 shows the current-voltage (I-V) characteristic of thep-type TFT and the n-type TFT of this embodiment. As shown in FIG. 11,p-type impurities are introduced into the gradient section in thechannel region more than the flat section so that the surface density ofp-type impurities in the gradient section is made to be substantiallyequal to that of the channel flat section. Accordingly, the threshold ofthe parasitic transistor formed at the gradient section of the channelregion becomes substantially equal to the threshold of the transistor atthe flat section, the hump in the I-V characteristic of the TFTdisappears, and both the n-type TFT and the p-type TFT turn off when thegate voltage is at 0V. Therefore, effects that leakage current of CMOSreduces and power consumption is significantly reduced can be obtained.

[0121] However, when the volume density of the p-type impurities in thegradient section in the channel region is smaller than approximatelytwice the volume density of the p-type impurities in the flat section,the threshold voltage of the n-type TFT is reduced by the influence bythe gradient section as in FIG. 2, and the n-type TFT does not turn offwhen the gate voltage is at 0V. On the other hand, when the volumedensity of the p-type impurities in the gradient section in the channelregion exceeds approximately five times the volume density of the p-typeimpurities in the flat section, the influence by the gradient sectionmoves the threshold voltage of the p-type TFT to a plus direction, andthe p-type TFT does not turn off when the gate voltage is at 0V.Therefore, it is required that the volume density of the p-typeimpurities in the gradient section in the channel region be twice tofive times the volume density of the p-type impurities in the flatsection.

[0122] In the above-described embodiment, although the amorphous siliconfilm containing the p-type impurities has been formed by the vapor-phasedoping method in the process shown in FIG. 8A and Fig.9A, the p-typeimpurities may be introduced into the amorphous silicon film by the ionimplantation method or the ion doping method after formation of anon-dope (impurities have not been introduced) amorphous silicon film.For example, the non-dope amorphous silicon film may be exposed toplasma of diborane gas to introduce the p-type impurities into theamorphous silicon film. Alternatively, the p-type impurities may beintroduced into the polysilicon film by the above-described method afterformation of the non-dope polysilicon film.

[0123] Furthermore, in the process shown in FIG. 8C and FIG. 9C,introduction of the p-type impurities into the gradient section of thepolysilicon film 123 has been performed by the ion doping method, but itmay be performed by using an ion implanter equipped with mass separationmechanism or an apparatus that introduces boron into a semiconductorfilm by plasma of diborane gas.

[0124] Moreover, the p-type impurities may be an element other thanboron (aluminum, for example). In this case, the p-type impurities ofthe element other than the one introduced into the polysilicon film 123in the process of FIG. 8A and 9A may be introduced into the gradientsection in the polysilicon film 123 in the process shown in FIG. 8C and9C.

[0125] Still further, when processing the polysilicon film 123 into anisland shape, the silicon oxide film may be formed on the polysiliconfilm 123 in the thickness of approximately 10 nm, for example, as aprotective film before forming the resist film R1 to preventcontamination caused by the resist film or the like.

[0126] Further, gas such as CF₄ and gas containing oxygen may be usedother than SF₆ as gas for etching the polysilicon film.

[0127] (Second Embodiment)

[0128]FIGS. 13A to 13C are the sectional views showing the manufacturingmethod of the thin film transistor device of the second embodiment ofthe present invention in the order of process.

[0129] First, as shown in FIG. 13A, the silicon oxide film is formed inthe thickness of approximately 100 nm as an underlying insulating film202 on a glass substrate 201.

[0130] Next, the amorphous silicon film containing boron (B), in thevolume density of 4×10¹⁷ cm⁻³, is formed on the underlying insulatingfilm 202 in the thickness of approximately 40 nm by the vapor-phasedoping method. Subsequently, excimer laser is irradiated over the entireupper surface of the substrate 201 to change the amorphous silicon filmto the polysilicon film 203. Then, a mask film 204 made up of thesilicon oxide film, for example, is formed on the polysilicon film 203in the thickness of approximately 25 nm. Although the mask film 204 isformed of insulator in this embodiment, it may be formed by conductivematerial. Further, the mask film 204 needs a thickness to the extentthat it can prevent implantation of the p-type impurities into the flatsection of the polysilicon film 203 in the process to introduce thep-type impurities into the gradient section of the polysilicon film 203(described later).

[0131] Next, a resist film R2 is formed on the mask film 204 in the TFTformation region using the positive type photoresist.

[0132] Then, the substrate is placed in the dry etching system, and CF₄and oxygen gas, for example, are introduced in the etching system toperform dry etching to the mask film 204 and the polysilicon film 203into the island shape as shown in FIG. 13B. At this point, gradientwhose width becomes smaller from the bottom portion to the upper portionis created at the edge portion of the resist film R2, and the gradientsection gradually withdraws as it is etched in plasma containing oxygen.With this withdrawal, gradient as shown in FIG. 13B is created at theedge portion of the polysilicon film 203 as well.

[0133] Next, as shown in FIG. 13C, after removal of the resist film R2by remover, boron (B) is implanted into the polysilicon film 203 usingthe ion doping system on condition that the acceleration voltage is 5 kVand the dosage is 2×10¹² cm⁻². Accordingly, boron is not introduced intothe flat section of the polysilicon film 203, which is masked by themask film 204, boron is introduced only into the gradient section of thepolysilicon film 203, which is exposed from the mask film 204. Thevolume density of boron in the gradient section of the polysilicon film203 is approximately 1×10¹⁸cm⁻³ together with the one introduced in thepolysilicon film 203 first. This density is equivalent to approximately2.5 times the volume density of boron at the channel center (flatsection) of the polysilicon film 203.

[0134] After having introduced boron only into the gradient section ofthe polysilicon film 203 in this manner, mask film 204 is removed. Sincethe subsequent process is the same as that of the first embodiment, itsdescription will be omitted here. In the case where the mask film 204 ismade up of the silicon oxide film as in this embodiment, the mask film204 is not removed but may be used as a part of the gate insulatingfilm.

[0135] In this embodiment, since the impurities are implanted into thegradient section of the polysilicon film 203 after the resist film R2has been removed, the surface of the resist film R2 does not causealteration due to implantation of the impurities, and thus the resistfilm R2 can be removed by remover. This makes a removal operation of theresist film easier comparing to the first embodiment. However, theresist film R2 may be removed by plasma ashing in this embodiment aswell.

[0136] Furthermore, in this embodiment, the amorphous silicon film intowhich the impurities have been introduced is formed and laser isirradiated on the amorphous silicon film, and the polysilicon film intowhich the impurities for controlling the threshold is thus formed.However, as shown in FIG. 14, the non-dope polysilicon film 203 isformed and the p-type impurities for controlling the threshold may beintroduced over the entire polysilicon film 203 by the ion doping methodor the like. For example, when boron is introduced in the entirepolysilicon film 203, the acceleration voltage and the dosage are set to25 kV and 3×10¹² cm⁻² respectively. Boron ion transmits through the maskfilm 204 and is implanted into the polysilicon film 203 under theseconditions. Further, when boron is introduced only into the gradientsection of the polysilicon film 203 (the portion protruded from the maskfilm 204), the acceleration voltage and the dosage are set to 5 kV and2×10¹² cm⁻² respectively.

[0137] As a result, the volume density of boron that the center (flatsection) of the polysilicon film 203 contains is approximately 4×10¹⁷cm⁻³ and the volume density of boron in the gradient section isapproximately 1×10¹⁸ cm⁻³.

[0138] Generally, when doping a small quantity of impurities into thesilicon film as in the case of controlling the threshold, the ion dopingmethod or the ion implantation method has superior controllability ofimpurities dosage comparing to the vapor-phase doping method usingdiborane gas, and can control the threshold of the TFT with goodaccuracy.

[0139] Furthermore, in this embodiment, boron (B) is implanted into thegradient section of the polysilicon film 203 by ion doping using themask film 204 as a mask. In the ion doping, since most ions areimplanted in the state of B₂ Hx⁺ (x is an integer), shallow implantationcan be performed comparing to the case where mass separation isperformed and implantation is performed in B⁺ ion, and therefore, themask film 204 can be used as a mask.

[0140] However, it is possible to adopt the ion implantation methodequipped with the mass separation mechanism by appropriately setting thethickness of the mask film 204 and the acceleration voltage.Furthermore, introduction of boron into the gradient section of thepolysilicon film 203 can be performed by plasma processing usingdiborane gas.

[0141] (Third Embodiment)

[0142]FIGS. 15A to 15C are the sectional views showing the manufacturingmethod of the thin film transistor device of the third embodimentaccording to the present invention in the order of process.

[0143] First, as shown in FIG. 15A, the silicon oxide film is formed inthe thickness of approximately 100 nm as an underlying insulating film222 on a glass substrate 221, in the same manner as the firstembodiment.

[0144] Next, the non-dope amorphous silicon film is formed on theunderlying insulating film 222 in the thickness of approximately 40 nm.Subsequently, excimer laser is irradiated over the entire upper surfaceof the glass substrate 221 to change the amorphous silicon film to thepolysilicon film 223. Then, a resist film R3 is formed on thepolysilicon film 223 in the TFT formation region using the positive typephotoresist.

[0145] Next, the substrate 221 is placed in the dry etching system, SF₆and oxygen gas, for example, are introduced in the dry etching system toperform etching to the polysilicon film 223 into the island shape. Atthis point, gradient whose width becomes smaller from the bottom portionto the upper portion is created at the edge portion of the resist filmR3, and the gradient surface gradually withdraws as it is etched inplasma containing oxygen. With this withdrawal, gradient is created atthe edge portion of the polysilicon film 223 as well as shown in FIG.15B.

[0146] Next, as shown in FIG. 15C, after removal of the resist film R3by remover, plasma ashing, or the like, boron is introduced into aportion close to the surface of the channel flat section and thegradient section of the polysilicon film 223 using the ion doping systemon condition that the acceleration voltage is 5 kV and the dosage is1.5×10² cm⁻².

[0147] Since the process after having introduced boron into the flatsection and the gradient section of the polysilicon film 223 in thismanner is the same as the first embodiment, its description will beomitted here.

[0148] In this embodiment, boron is introduced into the flat section andthe gradient section of the channel region of the polysilicon film 223such that a peak of distribution appears in the vicinity of the surfacethereof. This makes the surface density of boron in the flat section andthe gradient section of the channel region become substantially equal toeach other, and hump occurrence in the current-voltage (I-V)characteristic can be restricted. In addition, introduction of thep-type impurities into the flat section for controlling the thresholdand introduction of the p-type impurities into the gradient section forrestricting humps are performed in the same process, which prevents thenumber of process from increasing.

[0149] Note that boron has introduced into the vicinity of the surfaceof the polysilicon film 223 using the ion doping system in thisembodiment. However, the impurities may be introduced into the surfaceof the polysilicon film 223 by the ion implantation method or the plasmaprocessing using diborane gas.

[0150] Incidentally, to make controlling of the threshold easier, thep-type impurities for controlling the threshold is introduced into then-type TFT more than the p-type TFT, and the difference between thethreshold of the n-type TFT and the threshold of the p-type TFT can bemade large.

[0151] This technique can be used at the same time in any of the firstto the third embodiments. An example where the technique is applied forthe third embodiment will be described as follows.

[0152] In the process shown in FIG. 15C, the conditions when boron isintroduced into the portion close to the surface of the flat section andthe gradient section of the polysilicon film 223 are the accelerationvoltage of 5 kV and the dosage of 1×10¹² cm⁻².

[0153] Next, the resist mask, which covers the p-type TFT formationregion and which the n-type TFT formation region is exposed, is formedon the upper portion of the substrate 221. Then boron is implanted intothe polysilicon film in the n-type TFT formation region on conditionthat the acceleration voltage is 5 kV and the dosage is 1×10¹² cm⁻².

[0154] As a result, since the surface density of boron in polysiliconfilm 223 of the p-type TFT becomes 1×10¹² cm⁻², the threshold moves to aminus direction from the above-described case by approximately 0.5V to1V. On the other hand, because boron of 2×10¹² cm⁻² is introduced intothe polysilicon film 223 of the n-type TFT by two-time implantation, thethreshold increases by approximately 0.5V to 1V from the above-describedcase and the difference between the thresholds of the n-type TFT and thep-type TFT becomes larger by 1V to 2V. However, a resist mask process isadded when adopting such technique.

[0155]FIG. 16 is the view showing the current-voltage I-V characteristicwhen the quantity of p-type impurities in the channel region of then-type TFT is larger than the quantity of p-type impurities in thechannel region of the p-type TFT. As shown in FIG. 16, by making thequantity of p-type impurities in the channel region of the n-type TFTbecome larger than the quantity of p-type impurities in the channelregion of the p-type TFT, the threshold voltage of the n-type TFTincreases. Therefore, the quantity of the impurities in the channelsection can be easily controlled so as to turn off both of the p-typeTFT and the n-type TFT when the gate voltage is 0V.

[0156] (Fourth Embodiment)

[0157]FIGS. 17A to 17D are the sectional views showing the manufacturingmethod of the thin film transistor device of the fourth embodimentaccording to the present invention.

[0158] First, as shown in FIG. 17A, the silicon oxide film is formed inthe thickness of approximately 100 nm as an underlying insulating film242 on a glass substrate 241, in the same manner as the firstembodiment.

[0159] Next, the amorphous silicon film containing boron in the densityof 3×10¹⁷ cm⁻³ is formed on the underlying insulating film 242 in thethickness of approximately 40 nm. In this embodiment, the density ofboron in the amorphous silicon film is smaller comparing to the firstembodiment.

[0160] Subsequently, excimer laser is irradiated over the entire uppersurface of the substrate 241 to change the amorphous silicon film to apolysilicon film 243. Then, a mask film 244 made up of the silicon oxidefilm, for example, is formed in the thickness of approximately 25 nm onthe polysilicon film 243.

[0161] Next, a resist film R3 is formed on the mask film 244 in the TFTformation region using the positive type photoresist.

[0162] Then, the substrate 241 is placed in the dry etching system, CF₄and oxygen gas, for example, are introduced in the dry etching system toperform etching to the mask film 244 and the polysilicon film 243 intothe island shape. At this point, gradient whose width becomes smallerfrom the bottom portion to the upper portion is created at the edgeportion of the resist film R3, and the gradient surface graduallywithdraws as it is etched in plasma containing oxygen. With thiswithdrawal, gradient is created at the edge portion of the polysiliconfilm 243 as well as shown in FIG. 17B.

[0163] Next, the resist film R3 is removed by remover, plasma ashing, orthe like. Then, a resist film R4, which covers the p-type TFT formationregion and at which the n-type TFT is exposed, is formed as shown inFIGS. 17C and 17D.

[0164] Then, boron is introduced into the entire polysilicon film 243 inthe n-type TFT formation region using the ion doping system on conditionthat the acceleration voltage is 25 kV and the dosage is 1.6×10¹² cm⁻².Subsequently, boron is implanted only into the gradient section of thepolysilicon film 243 in the n-type TFT formation region on conditionthat the acceleration voltage is 5 kV and the dosage is 3×10¹² cm⁻².

[0165] Thus, boron is introduced in the channel region of the p-type TFTin the density of 3×10¹⁷ cm⁻³, and boron of approximately 5×10¹⁷ cm⁻³andapproximately 1.6×10¹⁸ cm⁻³ are introduced into the channel flat sectionof the n-type TFT and the channel gradient section of the n-type TFTrespectively. As a result, the difference between the thresholds of then-type TFT and the p-type TFT becomes larger by approximately 1V to 1.5Vcomparing to the first embodiment.

[0166] Next, the resist film R4 and the mask film 244 are removed. Sincethe subsequent process is the same as the first embodiment, itsdescription will be omitted here.

[0167] In this embodiment, the gate insulating film has been formed onthe polysilicon film 243 after removal of the mask film 244 as well.However, the mask film 244 may be kept as it is as a part of the gateinsulating film in the same manner as the second embodiment when themask film 244 is made up of insulating film such as the silicon oxidefilm.

[0168] In this embodiment, the p-type impurities for controlling humpsare selectively introduced only into the gradient section of thepolysilicon film in the n-type TFT formation region, so that the humpdoes not occur in the p-type TFT and margin for the dosage of the p-typeimpurities becomes large. Thus, the threshold can be easily controlled.Moreover, p-type impurities are introduced into the channel flat sectionof the n-type TFT more than the channel flat section of the p-type TFT,and thus the difference between the thresholds of the n-type TFT and thep-type TFT can be made to be large. This further facilitates thresholdcontrol.

[0169] In this case, introduction of the impurities into the polysiliconfilm may be performed by the ion implantation method, and introductionof the impurities into the gradient section of the polysilicon film maybe performed by plasma processing by diborane gas as well.

[0170] Further, although the amorphous silicon film containing thep-type impurities has been formed by the vapor-phase doping method inthis embodiment, the impurities may be introduced into the amorphoussilicon film by the ion implantation method or the ion doping methodafter having formed the non-dope amorphous silicon film. Furthermore,the impurities may be introduced into the polysilicon film by the ionimplantation method or the ion doping method after having formed thenon-dope poly silicon film.

[0171] The above-described first to fourth embodiments can be appliedfor the thin film transistor having the inversely staggered TFT. In thiscase, the semiconductor film is formed after the gate electrode and thegate insulating film have been formed. Although description has beenmade for the TFT where the operation layer was made up of thepolysilicon film in all of the first to fourth embodiments, the presentinvention can be also applied for the TFT where the operation layer ismade up of the amorphous silicon film or other types of semiconductorfilm.

[0172] Moreover, description has been made for the case where thepresent invention was applied for the liquid crystal display panel inall of the first to fourth embodiments, the present invention can bealso applied for the organic EL display panel or an apparatus usingother types of TFT.

What is claimed is:
 1. A thin film transistor device, comprising: asubstrate; and a thin film transistor that is formed above saidsubstrate and has a semiconductor film, where p-type impurities havebeen introduced in a channel region, as an active layer, whereingradient is provided for an edge portion of said semiconductor film andthe volume density of the p-type impurities in said edge portion of saidchannel region is twice to five times the volume density of the p-typeimpurities in a central section of said channel region.
 2. The thin filmtransistor device according to claim 1, wherein an n-type thin filmtransistor and a p-type thin film transistor are formed above saidsubstrate, and the p-type impurities have been introduced into channelregions of both said n-type thin film transistor and said p-type thinfilm transistor.
 3. The thin film transistor device according to claim2, wherein the volume density of the p-type impurities in the channelregion of said n-type thin film transistor is larger than the volumedensity of the p-type impurities in the channel region of said p-typethin film transistor.
 4. A method of manufacturing a thin filmtransistor device, comprising the steps of: forming a semiconductorfilm, into which p-type impurities have been introduced, above asubstrate; forming a resist film on a thin film transistor formationregion of said semiconductor film; etching said semiconductor film usingsaid resist film as a mask; introducing the p-type impurities into aportion of said semiconductor film, which has protruded from said resistfilm, using said resist film as a mask; removing said resist film;forming a gate insulating film; and forming a gate electrode.
 5. Themethod of manufacturing a thin film transistor device according to claim4, wherein said step of etching is performed by dry etching using anyone of gas containing SF₆ and oxygen, and gas containing CF₄ and oxygen.6. The method of manufacturing a thin film transistor device accordingto claim 4, further comprising the step of: etching said resist film towithdraw the edge portion of said resist film after said step ofetching.
 7. A method of manufacturing a thin film transistor device,comprising the steps of: forming a semiconductor film, into which p-typeimpurities have been introduced, above a substrate; forming a mask filmon said semiconductor film; forming a resist film on a thin filmtransistor formation region of said mask film; etching said mask filmand said semiconductor film using said resist film as a mask; removingsaid resist film; introducing the p-type impurities into a portion ofsaid semiconductor film, which has protruded from said mask film, usingsaid mask film as a mask; forming a gate insulating film; and forming agate electrode.
 8. The method of manufacturing a thin film transistordevice according to claim 7, wherein said gate insulating film is formedon said semiconductor film after removing said mask film.
 9. The methodof manufacturing a thin film transistor device according to claim 7,wherein said gate insulating film is formed on said semiconductor filmwhile using said mask film as a part of the gate insulating film. 10.The method of manufacturing a thin film transistor device according toclaim 7, wherein said step of etching is performed by dry etching usinggas containing CF₄ and oxygen.
 11. A method of manufacturing a thin filmtransistor device, comprising the steps of: forming a semiconductor filmabove a substrate; forming a mask film on said semiconductor film;forming a resist film on a thin film transistor formation region of saidmask film; etching said mask film and said semiconductor film using saidresist film as a mask; removing said resist film; introducing p-typeimpurities into the entire said semiconductor film on condition that theimpurities transmit through said mask film, and introducing the p-typeimpurities only into a part of said semiconductor film, which hasprotruded from said mask film, on condition that the impurities areblocked by said mask film; forming a gate insulating film; and forming agate electrode.
 12. The method of manufacturing a thin film transistordevice according to claim 11, wherein introduction of the p-typeimpurities into said semiconductor film is performed by any one of anion implantation method and an ion doping method.
 13. A thin filmtransistor device, comprising: a substrate; and a thin film transistorthat is formed above said substrate and has a semiconductor film, wherep-type impurities have been introduced at least into a channel region,as an operation layer, wherein gradient is provided for an edge portionof said semiconductor film and the p-type impurities have beenintroduced into a channel region of said semiconductor film such that apeak of distribution appears in the vicinity of a surface of the film.14. A method of manufacturing a thin film transistor device, comprisingthe steps of: forming a semiconductor film above a substrate; forming aresist film on a thin film transistor formation region of saidsemiconductor film; etching said semiconductor film using said resistfilm as a mask; removing said resist film; introducing p-type impuritiesinto said semiconductor film on condition that a peak of distributionappears in the vicinity of a surface of said semiconductor film; forminga gate insulating film; and forming a gate electrode.
 15. A thin filmtransistor device, comprising: a substrate; and a p-type thin filmtransistor and an n-type thin film transistor, which are formed abovesaid substrate, wherein both said p-type thin film transistor and saidn-type thin film transistor have a semiconductor film, which is providedwith gradient at an edge portion, as an operation layer, volume densityof the p-type impurities that the channel region of said semiconductorfilm of said n-type thin film transistor contains is higher than thevolume density of the p-type impurities in the channel region of saidsemiconductor film of said p-type thin film transistor, and the volumedensity of the p-type impurities in the gradient section of the channelregion of said n-type thin film transistor is twice or more the volumedensity of the p-type impurities in the central section of said channelregion.
 16. A method of manufacturing a thin film transistor device,comprising the steps of: forming a semiconductor film, into which p-typeimpurities have been introduced, above a substrate; forming a mask filmon said semiconductor film; forming a first resist film on a p-type thinfilm transistor formation region and an n-type thin film transistorformation region of said mask film; etching said semiconductor film andsaid mask film using said first resist film as a mask; removing saidfirst resist film; covering the p-type thin film transistor formationregion above said substrate with a second resist film; introducing thep-type impurities into the entire said semiconductor film of said n-typethin film transistor formation region on condition that the impuritiestransmit through said mask film, and introducing the p-type impuritiesinto a part of said semiconductor film of said n-type thin filmtransistor formation region, which has protruded from said mask film, oncondition that the impurities are blocked by said mask film; removingsaid second resist film; forming a gate insulating film; and forming agate electrode.